Semiconductor memory devices are generally divided into volatile semiconductor memory devices such as dynamic random access memory (DRAM) devices or static random access memory (SRAM) devices, and non-volatile semiconductor memory devices such as flash memory devices or electrically erasable programmable read only memory (EEPROM) devices. The volatile semiconductor memory device loses data stored therein when power is off. However, the non-volatile semiconductor memory device keeps stored data even if power is out.
Among the non-volatile semiconductor memory devices, the flash memory device has been widely employed in various electronic apparatuses such as a digital camera, a cellular phone, an MP3 player, etc. Since a programming process and a reading process of the flash memory device take a relatively long time, technologies to manufacture a novel semiconductor memory device, for example, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device or a phase-change random access memory (PRAM) device, have been constantly developed.
The phase-change memory device stores information using a resistance difference between an amorphous phase and a crystalline phase of a phase-change material layer composed of a chalcogenide compound, e.g., germanium-antimony-tellurium (GST). Particularly, the PRAM device may store data as states of “0” and “1” using a reversible phase transition of the phase-change material layer. The amorphous phase of the phase-change material layer has a large resistance, whereas the crystalline phase of the phase-change material layer has a relatively small resistance. In the PRAM device, a transistor formed on a substrate may provide the phase-change material layer with a reset current (Ireset) for changing the phase of the phase-change material layer from the crystalline state into the amorphous state. The transistor may also supply the phase-change material layer with a set current (Iset) for changing the phase of the phase-change material layer from the amorphous state into the crystalline state. This PRAM device is disclosed in U.S. Pat. No. 5,596,522, U.S. Pat. No. 5,825,046, U.S. Pat. No. 6,919,578, Korean Laid-Open Patent Publication No. 2004-100499 and Korean Laid-Open Patent Publication No. 2003-81900.
In the conventional PRAM device, however, the phase-change material layer may not have proper properties so that the PRAM device may not have desired electrical characteristics. For example, the phase-change material layer may be rapidly deteriorated, to thereby considerably reduce data retention characteristics of the PRAM device. Additionally, the PRAM device may have a relatively great ser resistance when the phase-change material layer includes a normal GST compound.
Considering the above-mentioned problems, a phase-change material layer has been formed using a chalcogenide compound doped into additional elements such as nitrogen in order to improve electrical characteristics of a PRAM device including the phase-change material layer. For example, Korean Laid-Open Patent Publication 2004-76225 discloses a phase-change memory device including a phase-change material layer composed of a GST compound doped with nitrogen.
FIGS. 1A to 1D are cross-sectional views showing a method of manufacturing the phase-change memory device according to the above Korean Laid-Open Patent Publication 2004-76225.
Referring to FIG. 1A, an isolation layer 3 is formed on a semiconductor substrate 1 using an isolation process. The isolation layer 3 is formed using oxide so as to define an active region of the semiconductor substrate 1.
A gate structure 15 is formed on the active region, and then a source region 18 and a drain region 21 are formed at portions of the active region adjacent to the gate structure 15. The gate structure 15 includes a gate oxide layer pattern 6, a gate electrode 9 and a gate spacer 12. Thus, a transistor is formed on the semiconductor substrate 1.
An insulating interlayer 24 is formed on the semiconductor substrate 1 to cover the gate structure 15. The insulating interlayer 24 is formed using oxide.
Referring to FIG. 1B, a contact holes (not shown) are formed through the insulating interlayer 24 by partially etching the insulating interlayer 24. The contact holes expose the source and the drain regions 18 and 21.
After a lower conductive layer (not shown) is formed on the insulating interlayer 24 to fill the contact holes, the lower conductive layer is polished until the insulating interlayer 24 is exposed. Hence, a first contact pad 27 and a second contact pad 30 are formed in the contact holes. The first pad 27 makes contact with the source region 18, and the second contact pad 30 locates on the drain region 21.
A lower insulation layer 33 is formed on the insulating interlayer 24 to cover the first and the second contact pads 27 and 30. The lower insulation layer 33 is formed using silicon oxide.
The lower insulation layer 33 is partially etched to form an opening 36 exposing the first contact pad 27.
Referring to FIG. 1C, an insulation layer (not shown) is formed on sidewalls of the opening 36, the first contact pad 27 and the lower insulation layer 33. Then, the insulation layer is anisotropically etched to form a spacer 39 on the sidewall of the opening 39. The spacer 39 adjusts a width of a first electrode 42 formed in the opening 36.
A first conductive layer (not shown) is formed on the first contact pad 27 and the lower insulation layer 33 to completely fill the opening 36. The first conductive layer is formed using a conductive material including nitrogen, carbon or metal.
The first conductive layer is removed until the lower insulation layer 33 is exposed to form the first electrode 42. The first electrode 42 filling the opening 36 is formed on the first contact pad 27.
A phase-change material layer 45 and a second conductive layer 48 are successively formed on the first electrode 42 and the lower insulation layer 33. The phase-change material layer 45 is formed using a GST compound containing nitrogen, The second conductive layer 48 is formed using conductive material including nitrogen, carbon or metal.
Referring to FIG. 1D, the second conductive layer 48 and the phase-change material layer 45 are patterned to form a phase-change material layer pattern 51 and a second electrode 54 on the first electrode 42, and the lower insulation layer 33. The phase-change material layer pattern 51 includes the GST compound having a composition of (AXB100-X)nN100-n, wherein A indicates tellurium (Te), selenium (Se), sulfide (S) or polonium (Po), B represents antimony (Sb), arsenic (As), tin (Sb), phosphor (P), silver (Ag), indium (In) or bismuth (Bi), X≦80, and 75≦n≦99.75.
An upper insulation layer 57 is formed on the lower insulation layer 33 to cover the phase-change material layer pattern 51 and the second electrode 54, and then the upper insulation layer 57 is partially etched to form a contact hole (not shown) exposing the second electrode 51.
An upper conductive layer (not shown) is formed on the upper insulation layer 57 to fill the contact hole. The upper conductive layer is polished until the upper insulation layer 57 is exposed so that a conductive plug 60 filling the contact hole is formed on the second electrode 54.
However, in the above-mentioned phase-change memory device having the phase-change material layer pattern of the GST compound doped with nitrogen, the phase-change memory device may have a considerably large initial writing current although a set resistance of the phase-change memory device may be decreased. To improve an integration degree of the phase-change memory device, a driving current of the phase-change memory device needs to be reduced. However, the set resistance of the phase-change memory device may be greatly increased in accordance with a reduction of the driving current thereof when the phase-change material layer pattern of the phase-change memory device includes the GST compound doped with nitrogen only. Further, the phase-change memory device of GST compound doped with nitrogen may not ensure good adhesion strength relative to the first electrode and the second electrode. Thus, the first electrode and/or the second electrode may be separated from the phase-change material layer pattern, and also an interface resistance between the first electrode and the phase-change material layer pattern or the second electrode and the phase-change material layer pattern may be undesirably reduced.